The present invention relates generally to a method for manufacturing a semiconductor device, and more particularly, to a device isolating method which facilitates fabrication of a high-density semiconductor device by minimizing the lateral expansion of a field oxide layer in a process of forming the field oxide layer to accomplish the electrical isolation between nearby devices.
Generally, in manufacturing a semiconductor device, thousands of individual transistor devices are formed on a single silicon substrate. These devices are interconnected by internal wiring to provide an integrated circuit or IC. Since all the transistors are formed on the same substrate, they should be electrically isolated while allowing for the interconnections of the internal wires. Otherwise, undesired electrical connections between the transistors occur, resulting in circuit shorts. Several methods for device isolation have been heretofore proposed, including local oxidation of silicon (LOCOS).
Recently, semiconductor device integration density has been rapidly increased owing to the development of high resolution semiconductor processing techniques. In order to achieve such increased integration densities, the dimensions of the circuit pattern of the semiconductor device have been reduced, thereby necessitating that the device isolating region, also be proportionally reduced. Therefore, the technique employed for device isolation is an important factor with respect to increasing integration density of a semiconductor device, because it initially determines the dimension of a region in which a device is formed. In large-capacity memory devices, the device isolating process is a major factor with respect to determining the minimum dimension of a memory cell.
One of the most well-known device isolating techniques is a LOCOS technique in which a thick field oxide layer is selectively grown on a semiconductor substrate to be used as the device isolating region. In the LOCOS technique, a pad oxide layer, a nitride layer, and other layers are formed on a semiconductor substrate, and then patterned to thereby expose part of the semiconductor substrate. The exposed part of the substrate is oxidized, using the remaining layers as a mask, to form a thick field oxide layer. The thick field oxide layer is the device isolating region, and is commonly referred to as a field region. A typical conventional field oxide layer formation technique using the LOCOS method will be described below referring to FIGS. 1, 2 and 3.
Referring to FIG. 1, a pad oxide layer 12 and a silicon nitride layer 14 are sequentially formed on the overall surface of a silicon substrate 10, and a photoresist pattern 16 is formed on the resultant structure by a conventional photolithographic process. The photoresist pattern 16 defines the window for forming a field oxide layer. Subsequently, the exposed portion of the nitride layer 14 is dry-etched, using the photoresist pattern 16 as a mask, to form an opening 9, through which impurity ions of the same conductivity type as that of silicon substrate 10 are implanted to form a channel-stop layer 18 for preventing field inversion. For instance, if semiconductor substrate 10 is doped with P-type impurities, boron ions (B.sup.+) or another trivalent ion can be used for the impurity ion.
With reference now to FIG. 2, after the photoresist pattern 16 is removed, the silicon substrate 10 is exposed in a wet-oxidation atmosphere, under a high temperature of about 900.degree. C. -1,100.degree. C., so as to form a SiO2 field oxide layer 19. Since the silicon nitride layer 14 functions as an oxidation resistant layer for protecting the substrate during the oxidation step, field oxide layer 19 is formed only in the region in which its surface is exposed via opening 9. The oxidation step is carried out by combining an oxidizing agent and silicon. During the oxidation process, the silicon of the substrate is consumed, and the field oxide layer is formed, while the surface of the original substrate is corroded. However, the oxidation reaction does not solely occur in the vertical direction. Since the oxidizing agent (oxygen) infiltrates the flanks of the pad oxide layer under the nitride layer to be combined with the silicon of the substrate surface, the oxide layer is also grown horizontally and corrodes the active region in which a transistor, resistor, and the like, are formed. This lateral growth of the field oxide layer, commonly referred to as bird's beak, results in a reduction of the active region (i.e., the device forming region), thereby unduly limiting the integration density of the semiconductor device. Particularly, in a ULSI memory device requiring an active region size below 0.8 .mu.m, due to the exceedingly elongated bird's beak, the conventional LOCOS method is no longer useful.
With reference now to FIG. 3, the silicon nitride layer 14 and the pad oxide layer 12 are sequentially removed to leave the field oxide layer 19 for device isolation. As discussed above, by comparing FIGS. 1 and 3, it should be noted that the size of the potential active region before the oxidation step for forming the field oxide layer 19 (see FIG. is significantly reduced after the oxidation step (see FIG. 3).
Because of the above-stated shortcomings, the conventional LOCOS method cannot be employed for manufacturing high-integration density semiconductor devices. In order to decrease the encroachment of the field oxide layer into the active region (in other words, in order to reduce the extension of the bird's beak), selective polysilicon oxidation (SEPOX) and polysilicon buffered LOCOS (PB-LOCOS) methods, which oxidize polysilicon during the formation of the field oxide layer so as to alleviate the extent of the encroachment, have been proposed. For example, in the method proposed by Hei in Japanese Patent laid-open publication No. 2-97038, a polysilicon layer on the silicon substrate and the silicon substrate are selectively oxidized to form field oxide layer.
In the PB-LOCOS method (sometimes called poly-buffered LOCOS or PBL), a polysilicon buffer layer is formed between the pad oxide layer and nitride layer of the conventional LOCOS method. Since the chief factor for bird's beak formation is the diffusion of oxygen into the silicon substrate through the pad oxide layer, the addition of the polysilicon buffer layer reduces the diffusion of oxygen through the pad oxide layer to thereby diminish the lateral corrosion of the active region.
In the SEPOX method, a polysilicon layer is interposed between the pad oxide layer and the nitride layer, and then the polysilicon layer is oxidized to form the field oxide layer. FIGS. 4, 5 and 6 are cross-sectional views for illustrating the conventional SEPOX method, which is explained below.
With reference now to FIG. 4, pad oxide layer 22, polysilicon layer 24 and nitride layer 26 are sequentially formed on silicon substrate 20, and nitride layer 26 is dry-etched to form opening 27 for the formation of the field region. Subsequently, impurity ions of the same conductivity type as that of the substrate are implanted through opening 27 to form channel-stop layer 28.
With reference now to FIG. 5, the exposed portion of the polysilicon layer 24 is oxidized by a wet oxidation process carried out at a high temperature, to thereby form field oxide layer 29.
With reference now to FIG. 6, nitride layer 26 and pad oxide layer 22 are removed to complete field oxide layer 29 to be used as the device isolating region.
Though the above-described PB-LOCOS and SEPOX techniques can greatly reduce the size of the bird's beak (a three-dimensional oxidation phenomenon) compared with the conventional LOCOS method, since the lateral corrosion problem still remains, problems with their implementation persist for high-density semiconductor devices. With these techniques, since the polysilicon layer is formed on the silicon substrate and is oxidized to form the field oxide layer, step coverage is decreased. Further, as in the conventional LOCOS method, since a wide channel-stop layer is formed after being self-aligned with the device active region, the breakdown voltage of the device is decreased, which precludes the channel-stop layer impurities from being implanted in high concentration, which results in a punch-through problem.
Meanwhile, the resolution of currently-used photolithography devices is another limitation in reducing the device isolating region. Such a limitation is a very serious problem in the manufacturing of a submicron-level semiconductor device. When the design goal is to reduce the device isolating region below 0.5 .mu.m, since the minimum value of the resolution of the photolithography device is greater than a 0.5.mu., it is impossible to achieve this design goal.
In order to overcome the limitations of photolithography technology, the side wall-masked isolation (SWAMI) technique has been proposed, wherein a spacer is added onto the sidewalls of the patterned nitride layer or buffer layer. Japanese patent laid-open publication No. 1-282839 (to Hei), and U.S. Pat. No. 4,897,364 disclose improvements of this technique. With Hei's technique, a polysilicon layer is used as a spacer. With the technique proposed in U.S. Pat. No. 4,897,364, a double polysilicon layer is used for controllable and uniform sidewall framing. Since such a spacer is formed by anistropic etching without using a patterned mask, the device isolating region can be reduced below the resolution limit of the photolithography equipment.
In addition, a polysilicon encapsulated local oxidation (PELOX) method has been proposed to effectively control the length of the bird's beak (see "Polysilicon Encapsulated Local Oxidation" by S.S. Roth et al., IEEE ELECTRON DEVICE LETTERS, vol. 12, No. 3, March 1991). In the PELOX method, a cavity formed along the periphery of the nitride layer is filled with polysilicon to control the length of the bird's beak during oxidation. However, though the PELOX method can effectively control bird's beak length, it is not so effective in reducing the overall length of the field oxide layer which is the device isolating region.